The present invention relates to a semiconductor memory, and principally to a technology effective for application to a so-called one-intersection type memory array having dynamic memory cells placed at intersecting points of word lines and bit lines and in which a large number of banks are provided.
As a result of an investigation subsequent to the completion of the present invention, Japanese Patent Application Laid-Open No. Hei 4(1992)-134691 (hereinafter called xe2x80x9cprior art 1xe2x80x9d), Japanese Patent Application Laid-Open No. Hei 2(1990)-289988 (hereinafter called xe2x80x9cprior art 2xe2x80x9d), Japanese Patent Application Laid-Open No. Hei 9(1997)-213069 (hereinafter called xe2x80x9cprior art 3xe2x80x9d), Japanese Patent Application Laid-Open No. Hei 4(1992)-6692 (hereinafter called xe2x80x9cprior art 4xe2x80x9d) and Japanese Patent Application Laid-Open No. Hei 9(1997)-246482 (hereinafter calledxe2x80x94xe2x80x9cPrior art 5xe2x80x9d), were discovered. The publications according to the prior arts 1 through 5 respectively disclose an arrangement in which information storage capacitors using MOS capacity are used and open bit-line type (one-intersection type or system) sense amplifiers are alternately disposed. However, these publications do not disclose or suggest a multibank-configured DRAM of the type provided by the invention.
There has been a continuing effort to reduce the cost of a dynamic RAM (hereinafter called simply xe2x80x9cDRAMxe2x80x9d). To this end, a reduction in chip size is most effective. A scale-own has heretofore been proposed to reduce the memory cell size. It is however necessary to change even the operating mode or system of a memory array to achieve a further reduction in cell size. By changing the operating mode of a memory array from a two-intersection type to a one-intersection type, the cell size can ideally be reduced to 75% by using the same design rule. However, the one-intersection type memory array has a problem in that array noise which appears on each bit line or the like is high as compared with the two-intersection type memory array.
On the other hand, a multibank-configured DRAM array has become of increasing importance in a Rambus DRAM and a logic-mixed DRAM to improve system performance. It has been revealed that when a one-intersection type multi-bank DRAM is configured, the one-intersection type memory array has a problem in that the array noise which appears on the bit line or the like is high as compared with the two-intersection type memory array as described above, and noise interference between adjacent mats presents a large problem for the multi-bank configuration. In addition to the above, an increase in chip area due to end mats, which is where sense amplifiers are alternately laid out under a one-intersection configuration, also offers a problem. Such problems have led to the realization of the present invention, which provides a method of solving these problems in a multibank-configured DRAM.
An object of the present invention is to provide a semiconductor memory having a multi-bank configuration, which has been implemented with a high integration and a high stabilization of its operation.
Another object of the present invention is to provide a semiconductor memory which provides ease of use while achieving high integration and high stabilization of its operation.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A typical one of the features of the invention disclosed in the present application will be described in brief as follows: A plurality of sense amplifier areas are placed alternately with respect to a plurality of memory array areas which extend along a first direction. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells provided so as to correspond to portions where the plurality of bit lines and the plurality of word lines intersect. A plurality of sense amplifiers are provided, each of which receives therein a pair of signals from each of the bit lines extending to one of the memory array areas on both sides adjacent to the respective sense amplifier areas and each of the bit lines extending to the other thereof. Respective word-line selecting timings or addresses are independently set with respect to two memory array areas spaced away from each other with two or more memory array areas interposed therebetween.
Another typical one of the features of the invention disclosed in the present application will be explained in brief as follows: A plurality of sense amplifier areas are placed alternately relative to a plurality of memory array areas placed along a first direction. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the first direction, a plurality of word lines provided along a second direction intersecting the first direction, and a plurality of memory cells respectively provided in association with portions where the plurality of bit lines and the plurality of word lines intersect. A plurality of sense amplifiers are provided, each of which receives therein a pair of signals from each of the bit lines extending to one of the memory array areas on both sides adjacent to the respective sense amplifier areas and each of the bit lines extending to the other thereof. The two memory array areas provided adjacent to each other constitute one of a plurality of banks. Respective word-line selecting addresses are independently set with respect to two banks spaced away from each other, with one of the plurality of banks interposed therebetween.